Recently, research related to semiconductor devices using a bi-state material, such as phase-change random access memory (PRAM) devices, ferroelectric RAM (FRAM) devices, resistive RAM (RRAM) devices, and magnetic RAM (MRAM) devices has been carried out. Particularly, for the purpose of realizing a high integration degree, semiconductor devices having nanowire channels including a bi-state material have been developed.
Methods of forming nanowires may be divided into a top-down method and a bottom-up method. Each of these methods has its own advantages and disadvantages. For example, in the top-down method, forming a nanowire at a desired position can be relatively simple, however, forming a nanowire smaller than a certain size may not be as simple, so a high integration degree may not be realized. In order address such disadvantages, a double-patterning method has been developed, however, performing the method can be complicated. In the bottom-up method, forming nanowires at desired positions in a desired arrangement may be difficult, even though forming nanowires having minute sizes can be relatively simple. Additionally, when a diode and a memory unit is formed by growing nanowires on a substrate, a process for patterning catalyst and a high temperature heat treatment process are performed on the same substrate, which may be difficult.